BIOGRAPHY

Prof. Helmut Graeb (IEEE Fellow since 2014) received the Dipl.-Ing., Dr.-Ing., and Habilitation degrees in electrical engineering from the Technical University of Munich (TUM), Munich, Germany, in 1986, 1993, and 2008, respectively. He was with Siemens Corporation, Munich, from 1986 to 1987, where he was involved in the design of DRAMs. Since 1987, he has been with the Chair of Electronic Design Automation, TUM, where he has been the Head of a research group since 1993.

Prof. Graeb was a recipient of the 2021 Best Doctoral Advisor and the 2020 Best Teaching Awards of the Department of ECE at TUM, of the 2008 Prize of the Information Technology Society (ITG), of the 2004 Best Teaching Award of the TUM EE Faculty Students Association, and of the Third Prize of the 1996 Munich Business Plan Contest. He has served as the Vice-President Publications of the IEEE Council on Electronic Design Automation, as Executive Committee Member of the ICCAD, as member or the Chair of the Analog Program Subcommittees of the ICCAD, DAC, and DATE conferences, as Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING and the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, and as member of the Technical Advisory Board of MunEDA GmbH Munich, which he co-founded. He is a member of VDE ITG and VDE/VDI-Society Microelectronics, Microsystems, and Precision Engineering, and of IEEE.

RESEARCH INTERESTS

His research interests are in design automation for analog and mixed-signal circuits, with particular emphasis on:

• Pareto optimization of analog circuits considering parameter tolerances
• Analog design for yield and reliability
• Hierarchical sizing of analog circuits
• Analog/mixed signal test design
• Discrete sizingof analog circuits
• Structural analysis of analog and digital circuits
• Analog layout synthesis

RESEARCH PROJECTS

• MEMS Design Constraints and Analog Layout Synthesis
• Reliability Considerations in Analog Synthesis
• Power-Down Verification and Analog Layout Synthesis
• Structure and Symmetry Path Analysis of Analog and Digital Integrated Circuits
• Sizing of Analog Integrated Circuits towards Lifetime Robustness
• Constraint-Based Layout-Driven Sizing of Analog Circuits
• Discrete Sizing of Analog Integrated Circuits
• Deterministic Hierarchical Placement of Analog Integrated Circuits

AWARDS

• Elevation to IEEE Fellow (2014)
• Award of the ITG (2008)
• Lecturer Award of the Student Council of the ECE Department of TUM (2004)
• Munich Business Plan Competition, 3rd prize (1996)
• 6 nominations for Best Paper Awards at DAC, ICCAD and DATE conferences (since 1993)

KEY PUBLICATIONS

He has published more than 200 papers, six of which were nominated for best papers at the Design Automation Conference (DAC), the International Conference on Computer-Aided Design (ICCAD), and the Design, Automation and Test in Europe (DATE) conference.

1. Zwerger M, Neuner M, Graeb H: “Analog Power-Down Synthesis”. IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD). 2017. GMM-Preis 2019.
   Abstract
2. Eick M, Strasser M, Kun Lu, Schlichtmann U, Graeb H: “Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits”. IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD). 2011. GMM-Preis 2012.
   Abstract
3. Graeb H (Ed.): “Analog Layout Synthesis – A Survey of Topological Approaches”. Springer. 2011; ISBN: 978-1-4419-6931-6.
   Abstract
4. Graeb H: “Analog Design Centering and Sizing”. Springer. 2007; ISBN 978-1-4020-6003-8.
   Abstract
5. Antreich K, Graeb H: “Circuit optimization driven by worst-case distances”. IEEE International Conference on Computer-Aided Design (ICCAD). 1991; Selected for “Best of ICCAD 20 Years of Excellence in CAD” 2002.
   Abstract