Assoc. Prof. Gwee Bah Hwee

Associate Professor


Tel: +65 6790 6861


Dr. Bah-Hwee Gwee received his BEng (Hons) degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from Nanyang Technological University (NTU), Singapore, in 1992 and 1998 respectively.

He was an Assistant Professor in School of EEE, NTU from 1999 to 2005 and has been an Associate Professor since 2005. He had held several school administrative committee appointments including Chairman of EEE Career Guidance Committee from 2000 – 2005, Chairman of EEE Outreach Committee from 2005 – 2009, Assistant Chair (Students) EEE from 2010 – 2014 and has been the Assistant Chair (Outreach) EEE since 2017.

He is the Deputy-Director of National Integrated Centre for Evaluation (NiCE). Dr. Gwee was the Principal Investigators (PIs) of a number of research projects including the ASEAN-European Union University Network Programme, Ministry of Education (MoE) Tier-1 and Tier-2, Defence Science Organisation, Defence Science and Technology Agency, Temasek Laboratories@NTU, A-STAR PSF, Cybersecurity Agency, National Research Foundation projects. He was also the co-PIs of DARPA (USA), NRF (SOCure), NRF (CHFA), NTU-Panasonic, NTU-Lingköping and GAP (Proof of Concept) Fund research projects. His total research grant is amounting to more than US$15m. He has filed 8 US patents in circuit design and hardware security, 5 of them have been granted by US PTO. His research interests include hardware security, hardware assurance, asynchronous circuit, machine learning and image processing. Dr Gwee was awarded Defence Technology Prize Team (R&D) category in 2016, TL@NTU Scientific Award, 2016, TL@NTU Best Publication Award in 2012 and the NTU EEE Teaching Excellence Award – Year 3 in 2013. He has co-founded 2 start-ups, Advanced Electroacoustics (2005) and Async2Secure (2020).

Dr. Gwee was the Chairman of IEEE Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016. He has been the members of IEEE Circuits and Systems Society (CASS) DSP, VSA and Bio-CAS Technical Committees (TC) since 2004. He was the Chairman of IEEE CASS DSP TC from 2018 – 2020. He has served in the Organizing Committees for IEEE BioCAS-2004, IEEE APCCAS-2006, Technical Program Chair for ISIC-2007, ISIC-2011, ISIC-2016 and served in the steering committee for IEEE APCCAS 2006 – 2008. He was the General Co-Chair of IEEE DSP 2018, IEEE SOCC 2019, IEEE ISICAS 2021 and will be the General Co-Chair of ISCAS 2026 (IEEE CAS Society flagship conference). He was the Associate Editor for journal of Circuits, Systems and Signal Processing (CSSP) from 2007 – 2012, IEEE Transactions on Circuits and Systems I – Regular Papers (T-CAS I) from 2012-2013 and IEEE Transactions on Circuits and Systems II – Express Brief (T-CAS II) from 2010 – 2011, from 2018 – 2019 and from 2020 – 2021. He serves in the editorial board of IEEE Circuits and Systems Magazine from 2021 – 2022. He was an IEEE Distinguished Lecturer for CAS Society from 2009 – 2010 and from 2017 – 2018. He was the keynote speaker of IEEE MCSoC 2021, IEEE PAINE 2020 and IEEE APCCAS 2020.


  • Asynchronous Circuits
  • Physical Hardware Attack
  • Hardware Assurance
  • Hardware Security
  • Machine Learning
  • Image Processing
  • Class-D Amplifiers


  • ASIC FA Phase 2
  • Project Hardware Assurance
  • Sub-Project 2 – Feasibility Study: A Hierarchy Extractor


  • Event-driven Spiking Neural Networks Using Asynchronous-Logic Network-on-chip Routers in Field Programmable Gate Array (FPGA)
  • Hardware Security Thrust (ii): Investigation and development of methods for analysing and evaluating hardware security mechanisms implemented in FPGAs and to carry out vulnerability analysis of such mechanisms
  • Object Detection and Product Segmentation
  • Project HASTE
  • Research Programme in Assuring Hardware Security by Design in Systems on Chip (SOCure)
  • Sub-project 3 – Exercisable Funding – Community Engagement
  • Sub-project 4 – Exercisable Funding – Security Risk Evaluation for Logic Locking


US 2013/0113522 A1: Asynchronous-Logic Circuit For Full Dynamic Voltage Control (2014)
Abstract: Pre-Charge Static Logic (PCSL), is an asynchronous-logic Quasi-Delay-Insensitive architecture based on Static-Logic, featuring fully-range Dynamic Voltage Scaling including robust operation in the sub-threshold voltage regime, with simultaneous low hardware overheads, high-speed and yet low power dissipation. The invented PCSL logic circuit achieves this by integration of the Request sub-circuit into the Static-Logic cell. During the initial phase, the output of Static-Logic cell (within the PCSL logic circuit) is pre-charged. During the evaluate phase, the Static-Logic cell computes the input and the PCSL logic circuit outputs the computation.

US 2020-0004992 A1: Hardware Security To Countermeasure Side-Channel Attacks (2022)
Abstract: A method and an apparatus for hardware security to countermeasure side-channel attacks are provided. The method or apparatus may introduce at least one redundant or partial redundant computation having a similar power dissipation profile or an electromagnetic emission profile when compared to that of a genuine operation for cryptographic devices, and/or to reorder the iterations of operations in a different sequence. The redundant or partial redundant computation may be performed by using a different password key and/or a different raw data (e.g., plaintext). The presence of the redundant or partial redundant computation would make side-channel attacks difficult in the sense that genuine or redundant/partial redundant operations are difficult to be clearly identified, hence serving as a countermeasure for hardware security.


  1. K.L. Chang, J.S. Chang, B.H. Gwee, K.S. Chong,. (2013). Synchronous-logic and Asynchronous-logic 8051 Microcontroller Cores for Powering the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects. IEEE Journal on Emerging and Selected Topics in Circuits and Systems,.
  2. T. Lin, K.S. Chong, J.S. Chang and B.H. Gwee. (2013). An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. IEEE Journal of Solid-State Circuits, 48(2), 573-586.
  3. Tong Lin, Kwen-Siong Chong, Joseph S. Chang, and Bah-Hwee Gwee,. (2012). A Robust Asynchronous Approach for Realizing Ultra-Low Power Digital Self-Adaptive VDD Scaling System. IEEE Subthreshold Microelectronics Conference, IEEE SubVt 2012, Waltham, Massachusetts, USA, (pp. 1 – 3).
  4. Yiqiong Shi, Bah-Hwee Gwee, Ye Ren, Thet Khaing Phone and Chan Wai Ting,. (2012). Extracting Functional Modules from Flattened Gate-Level Netlist. International Symposium on Communications and Information Technologies (ISCIT’2012), Gold Coast, Australia, (pp. 538 – 543).
  5. J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang,. (2012). An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2012, Seoul, Korea, (pp. 1835 – 1838).

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