BIOGRAPHY

Prof. Chang Chip Hong received his B.Eng. (Hons) from National University of Singapore in 1989, and his M.Eng. and Ph.D. from the School of Electrical and Electronic Engineering of Nanyang Technological University, Singapore in 1993 and 1998, respectively. Since 1999, he has been with the School of Electrical and Electronic Engineering, Nanyang Technological University where he is currently an Associate Professor. He holds concurrent appointments at the university as the Asistant Chair (Alumni) of the School of EEE since June 2008, Deputy Director of the Centre for High Performance Embedded Systems (CHiPES) since 2000, and the Program Director of the VLSI Design and Embedded Systems research group of the Centre for Integrated Circuits and Systems (CICS) since 2003. He has published three book chapters and more than 140 refereed international journal and conference papers. He is an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers from 2010-2011, an Editorial Advisory Board Member of the Open Electrical and Electronic Engineering Journal since 2007, an Editorial Board Member of the Journal of Electrical and Computer Engineering since 2008, and a technical reviewer for several prestigious international journals. He is appointed the Charter Fellow of Advisory Directorate International by the American Biographical Institute, Inc. (ABI) and listed in the Marquis Who’s Who in the World since 2008. He is a Senior Member of the IEEE and a Fellow of IET.

RESEARCH INTERESTS

• Watermarking for VLSI IP Protection
• Multiplierless Digital Filter Design and Synthesis
• Residue Number Systems, Redundant Binary and Modulo Arithmetic Circuits
• Low-power
• Low-voltage Arithmetic Circuits
• Design Automation of VLSI Digital Circuits and Digital Signal Processing.

KEY PUBLICATIONS

1. M. R. Meher, C. C. Jong, C. H. Chang. (2011). A high bit rate serial-serial multiplier with on-the-fly accumulation by asynchronous counters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(10), 1733-1745.
2. A. Cui, C. H. Chang, S. Tahar and A. A. Hamid. (2011). A robust FSM watermarking scheme for IP protection of sequential circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(5), 678-690.
3. R. Muralidharan and C. H. Chang. (2011). Radix-8 Booth encoded modulo 2^n-1 multipliers with adaptive delay for high dynamic range residue number system. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(5), 982-993.
4. Y. Shao and C. H. Chang. (2011). Bayesian separation with sparsity promotion in perceptual wavelet domain for speech enhancement and hybrid speech recognition. IEEE Transactions on Systems, Man, and Cybernetics – Part A: Systems and Humans, 41(2), 284-293.
5. C. H. Chang, R. K. Satzoda. (2010). A low error and high performance multiplexer-based truncated multiplier. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1767-1771.