BIOGRAPHY

Prof. Andreas Herkersdorf is a professor in the Department of Electrical and Computer Engineering and also affiliated to the Department of Informatics at Technical University of Munich (TUM). He received a Dr. degree from ETH Zurich, Switzerland, in Electrical Engineering in 1991. Between 1988 and 2003, he has been in technical and management positions with the IBM Research Laboratory in Rüschlikon, Switzerland.

Since 2003, Prof. Herkersdorf leads the Chair of Integrated Systems at TUM. Between 2014 and 2017, he has been elected as Dean of Study Affairs in the Department of Electrical and Computer Engineering. He is a senior member of the IEEE, member of the DFG (German Research Foundation) Review Board, member of the European Network on High Performance and Embedded Architecture and Compilation (HiPEAC) and serves as editor for Springer and De Gruyter journals for design automation and information technology.

RESEARCH INTERESTS

• Application-specific multi-processor architectures
• IP network processing
• Network on Chip and self-adaptive fault-tolerant computing

HONOURS & AWARDS

• IBM Outstanding Technical Achievement Award (2001)
• IBM Master Inventor (1998)
• Four IBM Innovation Achievement Awards (1996 – 2003)

KEY PUBLICATIONS

1. Mischa Möstl, Johannes Schlatow, Rolf Ernst, Nikil Dutt, Ahmed Nassar, Amir Rahmani, Fadi J. Kurdahi, Thomas Wild, Armin Sadighi, Andreas Herkersdorf, „Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS“, Proceedings of the  IEEE, Volume: 106 Issue: 9, 2018.
2. C. Herber, A. Saeed, A. Herkersdorf, “Design and Evaluation of a Low-Latency AVB Ethernet Endpoint based on ARM SoC”, 12th International Conference on Embedded Software and Systems (ICESS) 2015, New York, USA.
3. Richter, C. Herber, T. Wild, A. Herkersdorf, “Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance”, Journal of Systems Architecture, 2015.
4. Herkersdorf, H. Aliee, M. Engel, et al., “Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience”, Microelectronics Reliability, Elsevier, Vol. 54, February 2014.
5. Lankes, T. Wild, S. Wallentowitz, A. Herkersdorf, “Benefits of Selective Packet Discard in Networks-on-Chip”, ACM Transactions on Architecture and Code Optimization (TACO), Vol. 9, No. 2, Article No. 12, pp 1-21, June, 2012.